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MDT10F630
1. General Description
This 8-bit Micro-controller uses a fully static CMOS technology to achieve high speed, small size, low power and high noise immunity. On chip memory includes 1 K words of Flash ROM, and 128 bytes of EEPROM, and 64 bytes of static RAM. automotive to low power remote and toy, transmitters/receivers, controller, small pointing devices, chargers,
telecommunications processors, such as Remote instruments, automobile and PC peripheral ... etc.
4. Pin Assignment
2. Features
Fully CMOS static design 8-bit data bus On chip flash ROM size : MDT10F630 -- 1 K words Internal RAM size : MDT10F630 -- 64 bytes (64 general purpose registers) 128 bytes of EEPROM 37 single word instructions 14-bit instructions 8-level stacks Operating voltage : 2.3V ~ 5.5 V Watchdog timer with on-chip RC oscillator Interrupt capability Timer0 : 8-bit timer with 3-bit prescaler Timer1 : 16-bit timer with 2-bit prescaler One analog comparator module Sleep mode for power saving PA with port change wake-up interrupt Power-on Reset 12 I/O pins with their own independent direction control
MDT10F630P11 (DIP) MDT10F630S11 (SOP)
Vdd OSC1/PA5 OSC2/PA4 PA3 PC5 PC4 PC3 1 2 3 4 5 6 7 14 13 12 11 10 9 8 Vss PA0/CIN+ PA1/CINPA2/INT PC0 PC1 PC2
MDT10F630P13 (DIP) MDT10F630S13 (SOP)
Vdd OSC1/PA5 OSC2/PA4 /MCLR PC5 PC4 PC3 1 2 3 4 5 6 7 14 13 12 11 10 9 8 Vss PA0/CIN+ PA1/CINPA2/INT PC0 PC1 PC2
3. Applications
The application areas of this MDT10F630 range from appliance motor control and high speed
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MDT10F630
5. Order Information
ROM (Words) 1.0K 1.0K 1.0K 1.0K RAM EEPROM (Bytes) (Bytes) 64 64 64 64 128 128 128 128 Timer Package (8/16 bit) 1/1 1/1 1/1 1/1 14-DIP 14-DIP 14-SOP 14-SOP
Device MDT10F630P11 MDT10F630P13 MDT10F630S11 MDT10F630S13
I/O 12 11 12 11
Comparators 1 1 1 1
Remark Pin 4 is PA3 function Pin 4 is /MCLR external reset function Pin 4 is PA3 function Pin 4 is /MCLR external reset function
6. Block Diagram
EEPROM 128x8 Stack Eight Levels
8 bits
Flash ROM 1024 x14
10 bits
Comparator RAM 64 x8
PA3
14 bits
Program Counters
Instruction Register
Special Register
Port A
PA0~PA2 PA4~PA5 5 bits
Port C Instruction Decoder
Data 8bit
PC0~PC5 6 bits
Oscillator circuit
Control Circuit
D0~D7
TMR0 8 Bits TMR1 16 Bits
Power on Reset Power Down Reset Watchdog Timer Working Register ALU Status Register
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MDT10F630
7. Pin Function Description
Pin Name PA0/CIN+ I/O I/O Function Description Port A, TTL input level, with program pull_hi and interrupt on pin change. Comparator input. PA1/CINI/O Port A, TTL input level, with program pull_hi and interrupt on pin change. Comparator input. PA2/T0CK/INT/COUT I/O Port A, TTL input level, with program pull_hi and interrupt on pin change. Timer0 clock input. External interrupt. Comparator output. PA3/MCLR I Port A, TTL input level, with program interrupt on pin change. Master clear. Schmitt Trigger input level. PA4/OSC2/T1G I/O Port A, TTL input level, with program pull_hi and interrupt on pin change. Oscillator crystal output, in RC mode clock output Fosc/4 frequency. Timer1 gate. PA5/OSC1/T1CKI I/O Port A, TTL input level, with program pull_hi and interrupt on pin change. Oscillator crystal input/external clock source input. Timer1 clock input. PC0 ~ 5 Vdd Vss I/O Port C, TTL input level. Power supply Ground
8. Memory Map 8.1 Program memory : 0000H 0001H ~0003H 0004H 0005H Peripheral interrupt Vector Reset Vector
Program memory
03FFH
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MDT10F630
8.2 Register file map : Address BANK 0 00 01 02 03 04 05 06 07 08~09 0A 0B 0C 0D 0E 0F 10 11~14 15 16 17~18 19 1A 1B 1C 1D 1E~1F 64 20~5F General Register 60~7F Unimplemented memory location. Mapped in Bank 0 E0~FF A0~DF CMSTA VRSTA EEDATA EEADR EECON1 EECON2 PAPHR PAINTR TMR1L TMR1H T1STA INOSCR PSTA PCHLAT INTS PIFB1 PCHLAT INTS PIEB1 PORT C CPIO C IAR RTCC PCL STATUS MSR PORT A IAR TMR PCL STATUS MSR CPIO A Description Address BANK 1 80 81 82 83 84 85 86 87 88~89 8A 8B 8C 8D 8E 8F 90 91~94 95 96 97~98 99 9A 9B 9C 9D 9E~9F
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MDT10F630
(1). 00H or 80H : IAR ( Indirect Address Register) Use contents of MSR to address data memory (not a physical register) (2). 01H : RTCC (Timer0 Counter) 8-bit real time clock/counter (3). 02H or 82H : PCL (Program Counter Low Byte) Low order 8 bits of the Program Counter (PC) (4). 03H or 83H : STATUS (Status register) Bit 0 1 2 3 4 5 Symbol C HC Z /PF /TF page Carry bit Half Carry bit Zero bit Power loss Flag bit WDT time-out Flag bit Register page select bit : 0 : 00H --- 7FH 1 : 80H --- FFH 6--7 ---- General purpose bit Function
(5). 04H or 84H : MSR (Memory Select Register) Memory Bank Select Register : 0 : 00~7F (Bank0) 1 : 80~FF (Bank1)
MSR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Indirect Addressing Mode (6). 05H : Port A data output register Bit 7 Port A Bit 6 Bit 5 PA5 Bit 4 PA4 Bit 3 PA3 Bit 2 PA2 Bit 1 PA1 Bit 0 PA0
Bit 7-6 : Unimplemented Bit 5-0 : PA5~PA0, I/O Register (7). 06H : Unimplemented Register.
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MDT10F630
(8). 07H : Port C data output register Bit 7 Port C Bit 6 Bit 5 PC5 Bit 4 PC4 Bit 3 PC3 Bit 2 PC2 Bit 1 PC1 Bit 0 PC0
(9). 08 ~ 09H : Unimplemented Register. (10). 0AH or 8AH : Program counter high byte. Bit 7 PCHLAT (11). Bit 6 Bit 5 Bit 4 PCH4 Bit 3 PCH3 Bit 2 PCH2 Bit 1 PCH1 Bit 0 PCH0
0BH or 8BH : Interrupt control register. Bit 7 Bit 6 PEIE Bit 5 TIS Bit 4 INTS Bit 3 PAIE Bit 2 TIF Bit 1 INTF Bit 0 PAIF
INTS
GIS
GIS : Global Interrupt Enable Bit. 0 = Disable all interrupts 1 = Enable all un-masked interrupts PEIE : Peripheral Interrupt Enable Bit. 0 = Disable all peripheral interrupts 1 = Enable all peripheral interrupts TIS : TMR0 Overflow Interrupt Enable Bit. 0 = Disable the Timer0 interrupt 1 = Enable the Timer0 interrupt INTS : PA2/INT Interrupt Enable Bit. 0 = Disable the PA2/INT interrupt 1 = Enable the PA2/INT interrupt PAIE : PA Port Change Interrupt Enable Bit. 0 = Disable the PA port change interrupt 1 = Enable the PA port change interrupt TIF : TMR0 Overflow Interrupt Flag Bit. 0 = Timer0 did not overflowed 1 = Timer0 has overflowed (must be cleared in software) INTF : PA2/INT Interrupt Flag Bit. 0 = The PA2/INT interrupt did not occur 1 = The PA2/INT interrupt occurred PAIF : PA Port Change Interrupt Flag Bit. 0 = None of the PA5~0 pins have changed state 1 = When at least one of the PA5~0 pins changed state (must be cleared in software) (12). PIFB1 0CH : Peripheral interrupt register. Bit 7 Bit 6 Bit 5 EEIF -
Bit 4 -
Bit 3 CMIF
Bit 2 -
Bit 1 -
Bit 0 TMR1IF
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MDT10F630
EEIF : EEPROM Write Operation Interrupt Flag Bit. 0 = The EEPROM write operation is not completed or has not been start 1 = The EEPROM write operation completed (must be cleared in software) CMIF : Comparator Interrupt Flag Bit. 0 = Comparator input has not changed 1 = Comparator input has changed (must be cleared in software) TMR1IF : TMR1 Overflow Interrupt Flag Bit. 0 = Timer1 register did not overflow 1 = Timer1 register overflowed (must be cleared in software) (13). (14). 0DH : Unimplemented register. 0EH : TMR1L (The timer1 LSB register) The LSB of the 16-bit TMR1. 0FH : TMR1H (The timer1 MSB register) The MSB of the 16-bit TMR1. 10H : Timer1 control register. Bit 7 T1STA Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
(15).
(16).
TMR1GE T1CKPS1 T1CKPS1 T1OSCEN /T1SYNC TMR1CLK TMR1ON
TMR1GE : Timer1 Gate Enable Bit. If TMR1ON = 0 this bit is ignored If TMR1ON = 1 0 = Timer1 is on 1 = Timer1 is on if /T1G pin is low T1CKPS1 & T1CKPS0: Timer1 Input Clock Prescale Select bits. 0 0 = 1 : 1 Prescale value 0 1 = 1 : 2 Prescale value 1 0 = 1 : 4 Prescale value 1 1 = 1 : 8 Prescale value T1OSCEN : LF Oscillator Enable Bit. If INTOSC without CLKOUT oscillator is active : 0 = LP oscillator is off 1 = LP oscillator is enabled for Timer1 clock /T1SYNC : Timer1 External Clock Input Synchronization Control Bit. If TMR1CLK = 0 this bit is ignored Timer1 use internal clock If TMR1CLK = 1 0 = Synchronize external clock input 1 = Do not synchronize external clock input TMR1CLK : Timer1 Clock Source Select Bit. 0 = Select internal clock Fosc/4 1 = Select External clock from T1CKI pin (on rising edge) TMR1ON : TMR1 On Bit. 0 = Stop Timer1 1 = Enable Timer1 This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw P.7 2008/4 Ver. 1.0
MDT10F630
(17). (18). 11 ~ 18H : Unimplemented register. 19H : Comparator control register. Bit 7 CMSTA Bit 6 CMOUT Bit 5 Bit 4 CMOINV Bit 3 CMIS Bit 2 CMP2 Bit 1 CMP1 Bit 0 CMP0
CMOUT : Comparator Output Bit. When CMOINV = 0 1 = Vin+ > Vin- ; 0 = Vin+ < VinWhen CMOINV = 1 1 = Vin+< Vin- ; 0 = Vin+ > VinCMOINV: Comparator Output Inversion Bit. 0 = Output not inverted 1 = Output inverted CMIS: Comparator Input Switch Bit. When CMP2 ~ 0 = 110 or 101 : 0 = Vin- connects to CIN1 = Vin- connects to CIN+ CMP2 ~ 0: Comparator Mode Bits. 0 0 0 = Comparator reset (POR default value - low power) 0 0 1 = Comparator with output 0 1 0 = Comparator without output 0 1 1 = Comparator with output and internal reference (Cvref in 99H register) 1 0 0 = Comparator without output and with internal reference (Cvref in 99H register) 1 0 1 = Comparator multiplexed input with internal reference (Cvref in 99H register) and output 1 1 0 = Comparator multiplexed input with internal reference (Cvref in 99H register) 1 1 1 = Comparator off (lowest power)
(19). (20).
1A ~ 1FH : Unimplemented register. 81H : Option control register. Bit 7 Bit 6 IES Symbol Prescaler Value 000 001 010 011 100 101 110 111 Bit 5 TCS Bit 4 TCE Bit 3 PSC Function TMR0 rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 WDT rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 Bit 2 PS2 Bit 1 PS1 Bit 0 PS0
TMR Bit
/PAPH
2--0
PS2--0
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MDT10F630
Bit 3 4 5 6 7 Symbol PSC TCE TCS IES /PAPH Function Prescaler assignment bit : 0 -- PA2/INT 1 -- Watchdog Timer RTCC signal Edge : 0 -- Increment on low-to-high transition on PA2 pin 1 -- Increment on high-to-low transition on PA2 pin RTCC signal set : 0 -- Internal instruction cycle clock 1 -- Transition on PA2/INT pin PA2 interrupt edge select bit : 0 -- Interrupt on falling edge of PA2/INT pin 1 -- Interrupt on rising edge of PA2/INT pin Port A Pull-up Enable Bit : 0 -- PA0~2 & PA4~5 pull-up all enable 1 -- PA0~2 & PA4~5 pull-up all disable
(21).
85H : Port A input/output control register. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CPIO A (22). (23).
-
CPIO PA5 CPIO PA4 CPIO PA3 CPIO PA2 CPIO PA1 CPIO PA0
86H : Unimplemented register. 87H : Port A input/output control register. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CPIO C (24). (25).
-
CPIO PC5 CPIO PC4 CPIO PC3 CPIO PC2 CPIO PC1 CPIO PC0
88 ~ 89H : Unimplemented register. 8CH : Peripheral interrupt enable register. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 CMIE Bit 2 Bit 1 Bit 0 TMR1IE
PIEB1
EEIE
EEIE : EEPROM Write Operation Interrupt Enable Bit. 0 = Disable the EEPROM write complete interrupt 1 = Enable the EEPROM write complete interrupt CMIE : Comparator Interrupt Enable Bit. 0 = Disable the comparator interrupt 1 = Enable the comparator interrupt TMR1IE : TMR1 Overflow Interrupt Enable Bit. 0 = Disable the TMR1 overflow interrupt 1 = Enable the TMR1 overflow interrupt (26). 8DH : Unimplemented register.
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MDT10F630
(27). 8EH : Power control register. Bit 7 PSTA Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 PORB Bit 0 -
PORB : Power On Reset Status Bit. 0 = A power on reset occurred (must be set in software after a power on reset occurs) 1 = No power on reset occurred (28). (29). 8FH : Unimplemented register. 90H : MCU oscillator control register. Bit 7 INOSCR Bit 6 REG Bit 5 REG Bit 4 REG Bit 3 ECKIN Bit 2 OSO2E Bit 1 OSC2O Bit 0 OSCIN
Bit6 ~ 4 : Normal register bits. ECKIN : External Clock Input Enable Bit. 0 = Disable oscillator external clock input 1 = Enable oscillator external clock input (must be set in external oscillator of RC mode ) OSO2E : Both of Internal and external oscillator Enable Bit. 0 = Only use internal oscillator or external oscillator 1 = Internal and external (LF mode only) oscillator enable both OSC2O : OSC2/PA4 Oscillator Clock Output Enable Bit. 0 = Disable OSC2/PA4 oscillator clock output in internal or external of RC mode oscillator 1 = Enable OSC2/PA4 oscillator clock output in internal or external of RC mode oscillator OSCIN : MCU Internal Or external oscillator Select Bit. 0 = Default the MCU clock based on internal 4MHz oscillator 1 = The MCU clock based on external oscillator (type from option select), When internal 4MHz oscillator change to external oscillator must wait OST time 20ms. Example : change oscillator on external oscillator (oscillator type from option select) BSR STATUS, PAGE ; Set page 1 LDWI 01H ; Set W data is 01H STWR 10H ; Store 01H to register 90H (INOSCR) BCR STATUS, PAGE ; Set page 0 (30). 91 ~ 94H : Unimplemented register. (31). 95H : Port A pull_hi control register. Bit 7 PAPHR Bit 6 Bit 5 PAH5 Bit 4 PHA4 Bit 3 Bit 2 PHA2 Bit 1 PHA1 Bit 0 PHA0
Bit 5-4 & Bit 2-0 : Port A Pull_hi Control Bits 0 = Pull_hi disable 1 = Pull_hi enable
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MDT10F630
(32). 96H : Port A interrupt-on-change control register. Bit 7 PAINTR Bit 6 Bit 5 PINTA5 Bit 4 PINTA4 Bit 3 PINTA3 Bit 2 PINTA2 Bit 1 PINTA1 Bit 0 PINTA0
Bit 5-0 : Port A Interrupt-On-Change Control Bits 0 = Interrupt-on-change disable 1 = Interrupt-on-change enable (33). (34). 97 ~ 98H : Unimplemented register. 99H : Voltage reference control register. Bit 7 VRSTA CVREN Bit 6 Bit 5 CVRRS Bit 4 Bit 3 CVR3 Bit 2 CVR2 Bit 1 CVR1 Bit 0 CVR0
Bit 7 : Comparator Voltage Reference Enable Bit 0 = Comparator voltage reference disable 1 = Comparator voltage reference enable Bit 5 : Comparator Voltage Reference Range Select Bit 0 = High range ; CVref = Vdd/4 + (CVR3:CVR0/32)*Vdd 1 = Low range ; CVref = (CVR3:CVR0/24)*Vdd Bit 3-0 : Comparator Voltage Reference Value Selection When CVRRS = 0, CVref = Vdd/4 + (CVR3:CVR0/32)*Vdd When CVRRS = 1, CVref = (CVR3:CVR0/24)*Vdd (35). 9AH : EEPROM data register. Bit 7 EEDATA (36). EED7 Bit 6 EED6 Bit 5 EED5 Bit 4 EED4 Bit 3 EED3 Bit 2 EED2 Bit 1 EED1 Bit 0 EED0
9BH : EEPROM address register. Bit 7 Bit 6 EEAD6 Bit 5 EEAD5 Bit 4 EEAD4 Bit 3 EEAD3 Bit 2 EEAD2 Bit 1 EEAD1 Bit 0 EEAD0
EEADR (37).
-
9CH : EEPROM control register 1. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 WRERR Bit 2 WREN Bit 1 WR Bit 0 RD
EECON1
-
Bit 7~4 is unimplemented : Read as "0" WRERR : EEPROM Write Error Flag Bit. 0 = The EEPROM write operation completed 1 = The EEPROM write operation is prematurely terminated (any MCLR reset or any WDT reset during normal operation) This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw P.11 2008/4 Ver. 1.0
MDT10F630
WREN : EEPROM Write Enable Bit. 0 = Inhibits write to the data EEPROM 1 = Allows write cycles WR : Write Control Bit. 0 = Write cycle to the data EEPROM is complete 1 = Initiates a write cycle. (The bit is cleared by hardware once write is complete. The WR bit can only be set (not clear) in software.) RD : Read Control Bit. 0 = Does not initiate an EEPROM read. 1 = Initiates an EEPROM read (read takes once cycle. RD is cleared in hardwave. The RD bit can only be set (not clear) in software.) (38). 9DH : EEPROM control register 2. Bit 7 EECON2 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 -
Write only ; Read as "0" When write data to the EEPROM must write 55/H to EECON2, and writ AA/H to EECON2 then set WR bit; the EEPROM can write data inside for write each byte. Example : Data EEPROM Write BSR BCR BSR LDWI STWR LDWI STWR BSR (39). STATUS, PAGE INTS, GIS EECON1, WREN 55H EECON2 0AAH EECON2 EECON1,WR ; Select page 1 ; Disable interrupt ; Enable write ; Write 55/H ; Write AA/H ; Begin write
9E ~ 9FH : Unimplemented register.
9. Reset Condition for all Registers
Power-On Reset, Power range detector Reset 0000 0000 xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx --xx xxxx
Register IAR RTCC PCL STATUS MSR PORT A
Address 00h(80h) 01h 02h(82h) 03h(83h) 04h(84h) 05h
/MCLR or WDT Reset 0000 0000 uuuu uuuu 0000 0000 000# #uuu uuuu uuuu --uu uuuu
Wake-up from SLEEP uuuu uuuu uuuu uuuu 0000 0100 000# #uuu uuuu uuuu --uu uuuu
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MDT10F630
Register PORT C PCHLAT INTS PIFB1 TMR1L TMR1H T1STA CMSTA TMR CPIO A CPIO C PIEB1 PSTA INOSCR PAPHR PAINTR VRSTA EEDATA EEADR EECON1 EECON2 Address 07h 0Ah(8Ah) 0Bh(8Bh) 0Ch 0Eh 0Fh 10h 19h 81h 85h 87h 8Ch 8Eh 90h 95h 96h 99h 9Ah 9Bh 9Ch 9Dh Power-On Reset, Power range detector Reset --xx xxxx ---0 0000 0000 0000 0--- 0--0 xxxx xxxx xxxx xxxx -000 0000 -0-0 0000 1111 1111 --11 1111 --11 1111 0--- 0--0 ---- --#-000 0000 --11 -111 --00 0000 0-0- 0000 0000 0000 -000 0000 ---- x000 ---- ---/MCLR or WDT Reset --uu uuuu ---0 0000 0000 0000 0--- 0--0 uuuu uuuu uuuu uuuu -000 0000 -0-0 0000 1111 1111 --11 1111 --11 1111 0--- 0--0 ---- --u-000 0000 --11 -111 --00 0000 0-0- 0000 0000 0000 -000 0000 ---- #000 ---- ---Wake-up from SLEEP --uu uuuu ---u uuuu uuuu uuuu u--- u--u uuuu uuuu uuuu uuuu -uuu uuuu -u-u uuuu uuuu uuuu --uu uuuu --uu uuuu u--- u--u ---- --u-uuu uuuu --uu -uuu --uu uuuu u-u- uuuu uuuu uuuu -uuu uuuu ---- #uuu ---- ----
Note : " x "unknown; " u "unchanged; " - "unimplemented, read as "0"; "# "value depends on condition
10. Instruction Set
Mnemonic Operands 010000 00000000 010000 00000001 010000 00000010 010000 00000011 010000 00000rrr NOP CLRWT SLEEP TMODE CPIO R No operation Clear Watchdog timer Sleep mode Load W to TMODE register Control I/O port register None 0WT 0WT, stop OSC WTMODE WCPIO r /TF, /PF /TF, /PF None None Function
Instruction Code
Operation
Status
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MDT10F630
Instruction Code Mnemonic Operands 010001 1rrrrrrr 011000 trrrrrrr 111010 iiiiiiii 010111 trrrrrrr 011001 trrrrrrr 011010 trrrrrrr 011011 trrrrrrr 011100 trrrrrrr 011101 trrrrrrr 011110 trrrrrrr 010010 trrrrrrr 110100 iiiiiiii 010011 trrrrrrr 110101 iiiiiiii 010100 trrrrrrr 110110 iiiiiiii 011111 trrrrrrr 010110 trrrrrrr 010101 trrrrrrr STWR R LDR R, t LDWI I SWAPR R, t INCR R, t INCRSZ R, t ADDWR R, t SUBWR R, t DECR R, t DECRSZ R, t ANDWR R, t ANDWI I IORWR R, t IORWI I XORWR R, t XORWI I COMR R, t RRR R, t RLR CLRW CLRR BCR BSR R R, b R, b R, t Store W to register Load register Load immediate to W Swap halves register Increment register Increment register, skip if zero Add W and register Subtract W from register Decrement register WR Rt IW [R(0~3) R(4~7)]t R + 1t R + 1t W + Rt R Wt (R+/W+1t) R 1t None Z None None Z None C, HC, Z C, HC, Z Z None Z Z Z Z Z Z Z C C Z Z None None None None None None None C,HC,Z C,HC,Z None None Function Operation Status
Decrement register, skip if zero R 1t AND W and register AND W and immediate Inclu. OR W and register Inclu. OR W and immediate Exclu. OR W and register Exclu. OR W and immediate Complement register Rotate right register Rotate left register Clear working register Clear register Bit clear Bit set Bit Test, skip if clear Bit Test, skip if set Long CALL subroutine Long JUMP to address Return, place immediate to W Add immediate to W Subtract W from immediate Return from interrupt Return from subroutine R Wt I WW R Wt I WW R Wt I WW /Rt R(n) R(n-1), CR(7), R(0)C R(n)r(n+1), CR(0), R(7)C 0W 0R 0R(b) 1R(b) Skip if R(b)=0 Skip if R(b)=1 NPC, PC+1Stack NPC StackPC, IW PC+1PC, W+IW I-WW StackPC,1GIS StackPC
010000 1xxxxxxx 010001 0rrrrrrr 0000bb brrrrrrr 0010bb brrrrrrr 0001bb brrrrrrr 0011bb brrrrrrr 100nnn nnnnnnnn 101nnn nnnnnnnn 110001 iiiiiiii 110111 iiiiiiii 111000 iiiiiiii 010000 00001001 010000 00000100
BTSC R, b BTSS R, b LCALL N LJUMP N RTIW I ADDWI I SUBWI I RTFI RET
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MDT10F630
Note : W WT TMODE CPIO /TF /PF PC OSC Inclu. Exclu. AND : : : : : : : : : : : Working register Watchdog timer TMODE mode register Control I/O port register Timer overflow flag Power loss flag Program Counter Oscillator Inclusive `' Exclusive `' Logic AND `' R C Z / x I N b t : : 0: 1: : : : : : : : Bit position Target Working register General register General register address Carry flag Half carry Zero flag Complement Don't care Immediate data ( 8 bits ) Immediate address
HC :
11. Electrical Characteristics
(A) Operating Voltage & Frequency Vdd 2.3 V ~5.5 V Frequency0 Hz ~ 20 MHz
(B) Input Voltage @ Vdd5.0 V, Temperature25 Port PA, PC Vil /MCLR PA, PC Vih /MCLR Vss 2.0V 3.6V 0.8V Vdd Vdd Min Vss Max 0.8V
Threshold Voltage :
Port A, Port C Vth1.18 V /MCLR Vil1.2 V, Vih3.35 V (Schmitt Trigger)
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MDT10F630
(C) Output Voltage @ Vdd5.0 V, Temperature25 , the typical value as followings : PA,PC Port Ioh20.0 mA Iol20.0 mA Ioh5.0 mA Iol5.0 mA Voh3.4 V Vol0.5 V Voh4.2 V Vol0.13 V
(D) Leakage Current @ Vdd5.0 V, Temperature25 , the typical value as followings : Iil Iih (E) Sleep Current @WDTEnable, Temperature25 , the typical value as followings : Idd 0.6 A Idd 1.5 A Idd 3.4 A Idd 5.8 A Idd 7.3 A - 1.0 A + 1.0 A
Vdd2.3 V Vdd3.0 V Vdd4.0 V Vdd5.0 V Vdd5.5V
@WDTDisable, Temperature25 , the typical value as followings :
Vdd2.3 V Vdd3.0 V Vdd4.0 V Vdd5.0 V Vdd5.5 V
Idd 1.0 A Idd 1.0 A Idd 1.0 A Idd 1.0 A Idd 1.0 A
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MDT10F630
(F) Operating Current / Voltage Temperature25, the typical value as followings : (i) InRC 4MHz ; WDTDisable; @ Vdd5.0 V
Voltage/Frequency 2.3 V 3.0 V 4.0 V 5.0 V 5.5 V
InRC 4M 360 A 480 A 610 A 780 A 860 A
Sleep < 1.0A < 1.0 A < 1.0 A < 1.0 A < 1.0A
(ii)
OSC TypeRC ; WDTEnable; @ Vdd5.0 V
Cext. (F)
Rext. (Ohm) 4.7 K 10 K
Frequency (Hz) 9.98 M 5.38 M 1.19 M 568 K 192 K 121 K 5.2 M 2.69 M 588 K 280 K 95 K 59 K 1.87 M 920 K 200 K 95 K 32 K 20.2 K
Current (A) 2.0 mA 1.1 m 450 350 290 280 1.2 mA 700 360 310 280 275 580 400 290 270 265 260
3P
47 K 100 K 300 K 470 K 4.7 K 10 K
20P
47 K 100 K 300 K 470 K 4.7 K 10 K
100P
47 K 100 K 300 K 470 K
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MDT10F630
Cext. (F) Rext. (Ohm) 4.7 K 10 K 300P 47 K 100 K 300 K 470 K Frequency (Hz) 796 K 391 K 84 K 40 K 13.5 K 8.5 K Current (A) 390 320 270 260 255 250
(iii) OSC TypeLF (C=10 P); WDTDisable; 32K( C=50 P) Voltage/Frequency 2.3 V 3.0 V 4.0 V 5.0 V 5.5 V 32 K 58 A 89A 137A 196 A 250A 455 K 82A 128A 189A 272A 330A 1M 107A 163A 253A 349A 400A Sleep <1.0A <1.0A <1.0A <1.0A <1.0A
(iv)
OSC TypeXT (C=10 P); WDTEnable; Voltage/Frequency 2.3 V 3.0 V 4.0 V 5.0 V 5.5 V 1M 124A 200A 347A 564 A 790 uA 4M 270 A 393 A 613 A 866 A 1.1 mA 10 M 520 A 771 A 1.2 mA 1.65 mA 2.0 mA Sleep 0.6 A 1.5 A 3.4 A 5.8 A 7.3 A
(v)
OSC TypeHF (C=10 P ); WDTEnable Voltage/Frequency 2.3 V 3.0 V 4.0 V 5.0 V 5.5 V 4M 297A 441A 696 A 1.1mA 1.3mA 10 M 586 A 832A 1.26 mA 1.78 mA 2.2 mA 20 M x 1.43 mA 2.15 mA 3.02 mA 4.75 mA Sleep 0.6 A 1.5 A 3.4 A 5.8 A 7.3A
This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw P.18 2008/4 Ver. 1.0
MDT10F630
(G) Pull_High Resistance
@ Input Mode : Vdd5.0 V PORT Pull-High Resistance Rhi = 18K Pull-High Resistance Rho = 18K
@ Input Mode : Vdd3.0 V PORT Pull-High Resistance Rhi = 31K Pull-High Resistance Rho = 31K p.s. : It is only a reference value for the Pull High Resistance, and the accurate value of the Resistance depends on the various parameter of the Process. But the variation of the value will be not more than 20%. (H) Power Edge-detector Reset Voltage (Not in Sleep Mode), @ Vdd5.0 V Vpr 1.65 ~ 1.95 V Vpr Vdd (Power Supply)
(I) The basic WDT time-out cycle time @Temperature25 , the typical value as followings : Voltage (V) 2.3 3.0 4.0 5.0 5.5 Basic WDT time-out cycle time (ms) 25.9 22.1 19.4 17.8 16.7
This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw P.19 2008/4 Ver. 1.0

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